Nowadays, Integrated Circuits (ICs) are increasingly scaled down, and feature sizes thereof are becoming smaller continuously and thus are approaching the theoretical limit of photolithography systems. Therefore, there are typically serious distortions in an image formed on a wafer by photolithography, that is, Optical Proximity Effects (OPEs) occur. As the photolithography technology is facing more strict requirements and challenges, there has been proposed the Double Patterning Technology (DPT) which is able to enhance photolithography resolutions. In the DPT, a circuit pattern with a high density is divided into two separate patterns with lower densities, which are then respectively printed onto a target wafer.
Hereinafter, the line-and-cut DPT for making gates in the conventional semiconductor device manufacture process is described with reference to FIGS. 1-3.
FIG. 1 shows a part of a layout of devices formed on a wafer. As shown in FIG. 1, a pattern of lines 1001, corresponding to a gate pattern to be formed, is printed on the wafer by coating a photo resist, exposing the resist through a mask, and then developing the resist. Here, active regions 1002 on the wafer are also shown. The respective lines of the pattern 1001 are printed in parallel in a single direction, and have same or similar pitches and critical dimensions.
Next, as shown in FIG. 2, cuts 1003 are formed in the pattern of lines 1001 by a further exposure through a cut mask and then development. Thus, in the pattern 1001, gate patterns corresponding to different devices are separated from one another.
Finally, etching is carried out with the photo resist pattern 1001 having cuts 1003 formed therein to achieve gate structures corresponding to this pattern. FIG. 3 shows gates 1005 formed by the etching, and also gate spacers 1006 surrounding the respective gates 1005.
In the above process, a single exposure for forming the gate patterns is divided into two: one for exposing the pattern of lines 1001, and the other for exposing the cuts 1003. As a result, it is possible to reduce the demand for the photolithography and improve the line width control in the photolithography. Further, it is possible to eliminate many proximity effects and thus improve the Optical Proximity Correction (OPC). Furthermore, it is able to ensure a good channel quality and thus guarantee a high mobility for carries in channels.
After the gates 1005 are formed on the wafer by means of etching as described above, the gate spacers 1006 are formed to surround the gates. In FIG. 3, for sake of simplification, no spacer is shown at the uppermost and lowermost sides. However, it is to be noted that there are also spacers 1006 formed at those positions if some gates 1005 terminate at those positions. In one word, the spacers 1006 surround the respective gates 1005. Since there are the cuts 1003 in the gate patterns, the material of the spacers 1006 will enter inside the cuts 1003. Thus, respective spacers of gate patterns on two opposite sides of a cut 1003 may merge into each other, resulting in defects such as voids in the cut 1003. The defects such as voids occurring in the cuts 1003 will cause defects in a dielectric layer (for example, a dielectric layer 2004 as described below) subsequently formed thereon. Those defects will impact performances of resultant devices.
Besides, as shown in FIG. 4, after the formation of gates 2005 on a wafer 2000 and the formation of spacers 2006 surrounding the respective gates 2005 as described above, a dielectric layer 2004 may be deposited on the wafer to keep electrical isolations between respective devices. Here, to form contacts to the gates and sources/drains, it is possible to etch contact holes corresponding to the gates and the sources/drains in the dielectric layer 2004 and fill them with a conductive material such as metal so as to form contacts 2007a and 2007b. In FIG. 4, it is also shown that metal silicides 2008 are formed on the gates and the sources/drains to reduce contact resistance.
In the conventional process, all the contacts, including the contacts 2007a on the sources/drains and the contacts 2007b on the gates, are manufactured by etching the contact holes to their bottoms at one time and then filling the contact holes with the conductive material. This brings a strict requirement on the etching of the contact holes. For example, since the etching depth on the gate is different from that on the source/drain, a short is likely to occur between the gate and the contact hole. Further, since the etching depth on the source/drain is relatively large while the corresponding opening is relatively small (that is, the width to height ratio is relatively small), various problems, such as under-etching, voids in the filled metal, and the like, are likely to occur. Those restrict the selection of manufacture processes and cause greater parasitic resistances as well.
In view of the above, there is a need for a novel semiconductor device structure and a method for manufacturing the same.